HD61202U Datasheet, PDF (14/33 Pages) Hitachi Semiconductor – Dot Matrix Liquid Crystal GraphicDisplay Column Driver

HD61202U
Z Address Counter
The Z address counter generates addresses for outputting the display data synchronized with the common
signal. This counter consists of 6 bits and counts up at the fall of the CL signal. At the high level of FRM,
the contents of the display start line register is present at the Z counter.
Display Data Latch
The display data latch stores the display data temporarily that is output from display data RAM to the
liquid crystal driving circuit. Data is latched at the rise of the CL signal. The display on/off instruction
controls the data in this latch and does not influence data in dicsplay data RAM.
Liquid Crystal Display Driver Circuit
The combination of latched display data and M signal causes one of the 4 liquid crystal driver levels, V1,
V2, V3, and V4 to be output.
Reset
The system can be initialized by setting #$% terminal at low level when turning power on.
1. Display off
2. Set display start line register line 0.
While #$% is low level, no instruction except status read can be accepted. Therefore, execute other
instructions after making sure that DB4 = 0 (clear RESET) and DB7 = 0 (ready) by status read
instruction. The conditions of power supply at initial power up are shown in Table 2.
Table 2 Power Supply Initial Conditions
Item
Symbol
Min
Typ
Max
Unit
Reset time
t_RST
1.0
—
—
µs
Do not fail to set the system again because RESET during operation may destroy the data in all the
registers except on/off register and in RAM.
t_RST
RST VILC
Reset timing
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