HD61202U Datasheet, PDF (11/33 Pages) Hitachi Semiconductor – Dot Matrix Liquid Crystal GraphicDisplay Column Driver

HD61202U
Display On/Off Flip/Flop
The display on/off flip/flop selects one of two states, on state and off state of segments Y1 to Y64. In on
state, the display data corresponding to that in RAM is output to the segments. On the other hand, the
display data at all segments disappear in off state independent of the data in RAM. It is controlled by
display on/off instruction. #$% signal = 0 sets the segments in off state. The status of the flip/flop is
output to DB5 by status read instruction. Display on/off instruction does not influence data in RAM. To
control display data latch by this flip/flop, CL signal (display synchronous signal) should be input
correctly.
Display Start Line Register
The display start line register specifies the line in RAM which corresponds to the top line of LCD panel,
when displaying contents in display data RAM on the LCD panel. It is used for scrolling of the screen.
6-bit display start line information is written into this register by the display start line set instruction.
When high level of the FRM signal starts the display, the information in this register is transferred to the
Z address counter, which controls the display address, presetting the Z address counter.
X, Y Address Counter
A 9-bit counter which designates addresses of the internal display data RAM. X address counter (upper 3
bits) and Y address counter (lower 6 bits) should be set to each address by the respective instructions.
1. X address counter
Ordinary register with no count functions. An address is set by instruction.
2. Y address counter
An Address is set by instruction and is increased by 1 automatically by R/W operations of display
data. The Y address counter loops the values of 0 to 63 to count.
Display Data RAM
Stores dot data for display. 1-bit data of this RAM corresponds to light on (data = 1) and light off (data =
0) of 1 dot in the display panel. The correspondence between Y addresses of RAM and segment pins can
be reversed by ADC signal.
As the ADC signal controls the Y address counter, reversing of the signal during the operation causes
malfunction and destruction of the contents of register and data of RAM. Therefore, never fail to connect
ADC pin to V_CC or GND when using.
Figure 3 shows the relations between Y address of RAM and segment pins in the cases of ADC = 1 and
ADC = 0 (display start line = 0, 1/64 duty cycle).
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