HB288032MM1 Datasheet, PDF (46/80 Pages) Hitachi Semiconductor – MultiMediaCard 32 MByte

HB288032MM1
• Last host command - next host command timing diagram
After the last command, which does not force a response, has been sent, the host can continue sending the
next command after at least N_CC clock periods.
CMD
Host command
N_CC cycles
Host command
S T content CRC E Z * * * * * * Z S T content CRC E
Host active
Host active
Timing CMD_n End to CMD_n+1 Start (All Modes)
In the case the CMD_n command was a last identification command (no more response sent by a card), then
the next CMD_n+1 command is allowed to follow after at least N_CC +136 (the length of the R2 response)
clock periods.
• Data access timing
Data transmission starts with the access time delay t_AC (which corresponds to N_AC), beginning from the end
bit of the data address command. The data transfer stops automatically in case of a data block transfer or
by a transfer stop command.
Host command
N_CR cycles
CMD S T content CRC E Z Z P * * * P S T
Response
content CRC E
Host active
Card active
N_AC cycles
Read data
DAT Z Z Z * * * * Z Z Z Z Z Z P * * * * * * * * * * * P S D D D * * *
Card active
Data Read Timing (Data Transfer Mode)
• Data transfer stop command timing
The card data transmission can be stopped using the stop command. The data transmission stops
immediately with the end bit of the stop command.
CMD
DAT
Host command
N_CR cycles
S T content CRC E Z Z P * * * P S T
Response
content CRC E
Host active
Card active
D D D ******** D D D E Z Z **********************
Card active
Timing of Stop Command (CMD12, Data Transfer Mode)
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