HD66710 Datasheet, PDF (25/73 Pages) Hitachi Semiconductor – (Dot Matrix Liquid Crystal Display Controller/Driver)

HD66710
Timing Generation Circuit
The timing generation circuit generates timing signals for the operation of internal circuits such as
DDRAM, CGROM, CGRAM, and SEGRAM. RAM read timing for display and internal operation timing
by MPU access are generated separately to avoid interfering with each other. Therefore, when writing
data to DDRAM, for example, there will be no undesirable interferences, such as flickering, in areas
other than the display area.
Liquid Crystal Display Driver Circuit
The liquid crystal display driver circuit consists of 33 common signal drivers and 40 segment signal
drivers. When the character font and number of lines are selected by a program, the required common
signal drivers automatically output drive waveforms, while the other common signal drivers continue to
output non-selection waveforms.
Character pattern data is sent serially through a 40-bit shift register and latched when all needed data has
arrived. The latched data then enables the driver to generate drive waveform outputs.
Sending serial data always starts at the display data character pattern corresponding to the last address of
the display data RAM (DDRAM).
Since serial data is latched when the display data character pattern corresponding to the starting address
enters the internal shift register, the HD66710 drives from the head display.
Cursor/Blink Control Circuit
The cursor/blink (or white-black inversion) control is used to produce a cursor or a flashing area on the
display at a position corresponding to the location in stored in the address counter (AC).
For example (Figure 10), when the address counter is 08H, a cursor is displayed at a position
corresponding to DDRAM address 08H.
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