HD66710 Datasheet, PDF (12/73 Pages) Hitachi Semiconductor – (Dot Matrix Liquid Crystal Display Controller/Driver)

HD66710
Function Description
Registers
The HD66710 has two 8-bit registers, an instruction register (IR) and a data register (DR).
The IR stores instruction codes, such as display clear and cursor shift, and address information for the
display data RAM (DDRAM), the character generator RAM (CGRAM), and the segment RAM
(SEGRAM). The MPU can only write to IR, and cannot be read from.
The DR temporarily stores data to be written into DDRAM, CGRAM, or SEGRAM. Data written into the
DR from the MPU is automatically written into DDRAM, CGRAM, or SEGRAM by an internal
operation. The DR is also used for data storage when reading data from DDRAM, CGRAM, or
SEGRAM. When address infor-mation is written into the IR, data is read and then stored into the DR
from DDRAM, CGRAM, or SEGRAM by an internal operation. Data transfer between the MPU is then
completed when the MPU reads the DR. After the read, data in DDRAM, CGRAM, or SEGRAM at the
next address is sent to the DR for the next read from the MPU. By the register selector (RS) signal, these
two registers can be selected (Table 2).
Busy Flag (BF)
: ^{When the busy flag is 1, the HD66710 is in the internal operation mode, and the next instruction will not}
be accepted. When RS = 0 and R/ = 1 (Table 2), the busy flag is output from DB7. The next instruction
must be written after ensuring that the busy flag is 0.
Address Counter (AC)
The address counter (AC) assigns addresses to DDRAM, CGRAM, or SEGRAM. When an address of an
instruction is written into the IR, the address information is sent from the IR to the AC. Selection of
DDRAM, CGRAM, and SEGRAM is also determined concurrently by the instruction.
: ^{After writing into (reading from) DDRAM, CGRAM, or SEGRAM, the AC is automatically incremented}
by 1 (decremented by 1). The AC contents are then output to DB0 to DB6 when RS = 0 and R/ = 1
(Table 2).
Table 2 Register Selection
RS
: R/
Operation
0
0
IR write as an internal operation (display clear, etc.)
0
1
Read busy flag (DB7) and address counter (DB0 to DB6)
1
0
DR write as an internal operation (DR to DDRAM, CGRAM, or SEGRAM)
1
1
DR read as an internal operation (DDRAM, CGRAM, or SEGRAM to DR)
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