HMNR28D Datasheet, PDF (7/13 Pages) Hanbit Electronics Co.,Ltd – 5.0 or 3.3V, 16K bit (2 Kbit x 8) TIMEKEEPER NVSRAM

HANBit
HMNR28D(V)
WRITE Mode
The HMNR28D(V) is in the WRITE Mode whenever /WE (WRITE Enable) and /CE (Chip Enable) are low state after the
address inputs are stable. The start of a WRITE is referenced from the latter occurring falling edge of /WE or /CE. A
WRITE is terminated by the earlier rising edge of /WE or /CE. The addresses must be held valid throughout the cycle. /CE
or /WE must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of
another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward.
/OE should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a
low on /CE and /OE a low on /WE will disable the outputs tWLQZ after /WE falls.
WRITE AC Waveforms, WRITE Enable Controlled
A0-A10
WRITE AC Waveforms, Chip Enable Controlled
A0-A10
URL : www.hbe.co.kr
Rev. 0.0 (March, 2002)
7
HANBit Electronics Co.,Ltd.