HMNR28D Datasheet, PDF (6/13 Pages) Hanbit Electronics Co.,Ltd – 5.0 or 3.3V, 16K bit (2 Kbit x 8) TIMEKEEPER NVSRAM

HANBit
HMNR28D(V)
READ Mode
The HMNR28D(V) is in the READ Mode whenever /WE (WRITE Enable) is high and /CE (Chip Enable) is low. The unique
address specified by the 15 Address Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data
will be available at the Data I/O pins within Address Access Time (tAVQV) after the last address input signal is stable,
providing the /CE and /OE access times are also satisfied. If the /CE and /OE access times are not met, valid data will be
available after the latter of the Chip Enable Access Times (tELQV) or Output Enable Access Time (tGLQV). The state of the
eight three-state Data I/O signals is controlled by /CE and /OE. If the outputs are activated before tAVQV, the data lines will
be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while /CE and /OE remain active, output
data will remain valid for Output Data Hold Time (tAXQX) but will go indeterminate until the next Address Access.
READ Mode AC Waveforms
A0-A10
/CE
/OE
Note : /WE = High.
READ Mode AC Characteristics
Symbol
Parameter
HMNR28D
HMNR28DV
-70
-85
Unit
Min
Max
Min
Max
tAVAV
READ Cycle Time
70
85
nS
tAVQV
Address Valid to Output Valid
70
85
nS
tELQV
Chip Enable Low to Output Valid
70
85
nS
tGLQV
Output Enable Low to Output Valid
tELQX(2)
Chip Enable Low to Output Transition
5
tGLQX(2)
Output Enable Low to Output Transition
0
tEHQZ(2)
Chip Enable High to Output Hi-Z
tGHQZ(2)
Output Enable High to Output Hi-Z
25
35
nS
5
nS
0
nS
20
25
nS
20
25
nS
tAXQX
Address Transition to Output Transition
5
5
nS
Note: 1.Valid for Ambient Operating Temperature: TA = 0 to 70° C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF.
URL : www.hbe.co.kr
Rev. 0.0 (March, 2002)
6
HANBit Electronics Co.,Ltd.