GS8182Q36BGD-167 Datasheet, PDF (8/36 Pages) GSI Technology – 18Mb SigmaQuad-IITM Burst of 2 SRAM

GS8182Q08/09/18/36BD-333/300/250/200/167/133
SigmaQuad-II B2 SRAM DDR Write
The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of
K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is
clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on
the rising edge of K along with the write address. Clocking in a high on W causes a write port deselect cycle.
SigmaQuad-II B2 Double Data Rate SRAM Write First
Write A
Read B
Read C Write D
NOP
Read E Write F
Read G Write H
NOP
K
K
Address
R
W
BWx
D
C
C
Q
CQ
CQ
A
B
C
D
E
F
G
H
A
A+1
A
A+1
D
D+1
D
D+1
F
F+1
H
H+1
F
F+1
H
H+1
B
B+1
C
C+1
E
E+1
Rev: 1.03d 11/2011
8/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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