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GS8182Q36BGD-167 Datasheet, PDF (17/36 Pages) GSI Technology – 18Mb SigmaQuad-IITM Burst of 2 SRAM
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GS8182Q08/09/18/36BD-333/300/250/200/167/133
HSTL I/O DC Input Characteristics
Parameter
Symbol
Min
Max
Units
Notes
DC Input Logic High
VIH (dc)
VREF + 0.1
VDDQ+ 0.3
V
1, 4
DC Input Logic Low
VIL (dc)
–0.3
VREF – 0.1
V
1, 3
Notes:
1. Compatible with both 1.8 V and 1.5 V I/O drivers.
2. These are DC test criteria. DC design criteria is VREF ± 50 mV. The AC VIH/VIL levels are defined separately for measuring timing
parameters.
3. VIL (Min)DC = –0.3 V, VIL(Min)AC = –1.5 V (pulse width ≤ 3 ns).
4. VIH (Max)DC = VDDQ + 0.3 V, VIH(Max)AC = VDDQ + 0.85 V (pulse width ≤ 3 ns).
HSTL I/O AC Input Characteristics
Parameter
Symbol
Min
Max
Units
AC Input Logic High
VIH (ac)
VREF + 200
—
mV
AC Input Logic Low
VIL (ac)
—
VREF – 200
mV
VREF Peak-to-Peak AC Voltage
VREF (ac)
—
5% VREF (DC)
mV
Notes:
1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other.
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
Notes
2, 3
2, 3
1
Undershoot Measurement and Timing
VIH
VSS
50%
VSS – 1.0 V
20% tKHKH
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 1.8 V)
Parameter
Input Capacitance
Output Capacitance
Clock Capacitance
Note:
This parameter is sample tested.
Symbol
CIN
COUT
CCLK
Overshoot Measurement and Timing
VDD + 1.0 V
50%
20% tKHKH
VDD
VIL
Test conditions
VIN = 0 V
VOUT = 0 V
VIN = 0 V
Typ.
Max.
Unit
4
5
pF
6
7
pF
5
6
pF
Rev: 1.03d 11/2011
17/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology
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