GS8182Q36BGD-167 Datasheet, PDF (6/36 Pages) GSI Technology – 18Mb SigmaQuad-IITM Burst of 2 SRAM

GS8182Q08/09/18/36BD-333/300/250/200/167/133
Pin Description Table
Symbol
Description
Type
Comments
SA
Synchronous Address Inputs
Input
—
NC
No Connect
—
—
R
Synchronous Read
Input
Active Low
W
Synchronous Write
Input
Active Low
BW
Synchronous Byte Write
Input
Active Low
x9 only
BW0–BW3
Synchronous Byte Writes
Input
Active Low
x36 only
BW0–BW1
Synchronous Byte Writes
Input
Active Low
x18 only
K
Input Clock
Input
Active High
K
Input Clock
Input
Active Low
C
Output Clock
Input
Active High
C
Output Clock
Input
Active Low
TMS
Test Mode Select
Input
—
TDI
Test Data Input
Input
—
TCK
Test Clock Input
Input
—
TDO
Test Data Output
Output
—
V_REF
HSTL Input Reference Voltage
Input
—
ZQ
Output Impedance Matching Input
Input
—
Qn
Synchronous Data Outputs
Output
—
Dn
Synchronous Data Inputs
Input
—
D_off
Disable DLL when low
Input
Active Low
CQ
Output Echo Clock
Output
—
CQ
Output Echo Clock
Output
—
V_DD
Power Supply
Supply
1.8 V Nominal
V_DDQ
Isolated Output Buffer Supply
Supply
1.5 or 1.8 V Nominal
V_SS
Power Supply: Ground
Supply
—
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to V_DDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. K, K cannot be set to V_REF voltage.
Rev: 1.03d 11/2011
6/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology