GS82582DT21 Datasheet, PDF (7/27 Pages) GSI Technology – 288Mb SigmaQuad-II+ Burst of 4 SRAM

GS82582DT21/39GE-675S/633S/550S
Separate I/O SigmaQuad II+ B4 SRAM Truth Table
Previous
Operation
SA
R
W
Current
Operation
D
Q
K
(t_n-1)
Deselect
K K K
(t_n) (t_n) (t_n)
X11
K
(t_n)
Deselect
K
(t_n+1)
X
K
(t_n+1½)
X
K
(t_n+2)
—
K
(t_n+2½)
—
K
(t_n+3)
Hi-Z
K
(t_n+3½)
Hi-Z
K
(t_n+4)
—
Write
X1X
Deselect
D2
D3
—
—
Hi-Z Hi-Z
—
Read
XX1
Deselect
X
X
—
—
Q2
Q3
—
Deselect V 1 0
Write
D0
D1
D2
D3
Hi-Z Hi-Z
—
Deselect V 0 X
Read
X
X
—
—
Q0
Q1
Q2
Read
VX0
Write
D0
D1
D2
D3
Q2
Q3
—
Write
V0X
Read
D2
D3
—
—
Q0
Q1
Q2
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
5. Users should not clock in metastable addresses.
K
(t_n+4½)
—
—
—
—
Q3
—
Q3
Rev: 1.01 4/2016
7/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology