GS82582DT21 Datasheet, PDF (6/27 Pages) GSI Technology – 288Mb SigmaQuad-II+ Burst of 4 SRAM

GS82582DT21/39GE-675S/633S/550S
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II+ SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
V_SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175 and 350. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Input Termination Impedance Control
These SigmaQuad-II+ SRAMs are supplied with programmable input termination on Data (D), Byte Write (BW), and Clock (K,K)
input receivers. The input termination is always enabled, and the impedance is programmed via the same RQ resistor (connected
between the ZQ pin and V_SS) used to program output driver impedance, in conjunction with the ODT pin (6R). When the ODT pin
is tied Low, input termination is "strong" (i.e., low impedance), and is nominally equal to RQ*0.3 Thevenin-equivalent when RQ is
between 175Ω and 350Ω. When the ODT pin is tied High (or left floating—the pin has a small pull-up resistor), input termination
is "weak" (i.e., high impedance), and is nominally equal to RQ*0.6 Thevenin-equivalent when RQ is between 175Ω and 250Ω.
Periodic readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same
manner as for driver impedance (see above).
Note:
Data (D), Byte Write (BW), and Clock (K, K) input termination is always enabled. Consequently, D, BW, K, K inputs should
always be driven High or Low; they should never be tri-stated (i.e., in a High-Z state). If the inputs are tri-stated, the input
termination will pull the signal to V_DDQ/2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver to
enter a meta-stable state, resulting in the receiver consuming more power than it normally would. This could result in the device’s
operating currents being higher.
Power-Up Initialization
After power-up, stable input clocks must be applied to the device for 20s prior to issuing read and write commands. See the tInit
timing parameter in the AC Electrical Characteristics section.
Note:
The tInit requirement is independent of the tLock requirement, which specifies how many cycles of stable input clocks (2048) must
be applied after the Doff pin has been driven High in order to ensure that the DLL locks properly (and the DLL must lock properly
before issuing read and write commands). However, tInit is greater than tLock, even at the slowest permitted cycle time of 8.4ns
(2048*8.4ns = 17.2s). Consequently, the 20s associated with tInit is sufficient to cover the tLock requirement at power-up if the
Doff pin is driven High prior to the start of the 20s period.
Also, tInit only needs to be met once, immediately after power-up, whereas tLock must be met any time the DLL is disabled / reset
(whether by toggling Doff Low or by stopping K clocks for > 30ns).
Rev: 1.01 4/2016
6/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology