GS82582DT21 Datasheet, PDF (15/27 Pages) GSI Technology – 288Mb SigmaQuad-II+ Burst of 4 SRAM

GS82582DT21/39GE-675S/633S/550S
AC Electrical Characteristics
Parameter
Clock
K, K Clock Cycle Time
Symbol
t_KHKH
-675S
Min
Max
1.48
8.4
-633S
Min
Max
1.58
8.4
-550S
Min
Max
1.81
8.4
ns
K, K Clock Phase Jitter
t_KVar
—
0.15
—
0.15
—
0.15
ns 3
K, K Clock High Pulse Width
t_KHKL
0.45
—
0.45
—
0.45
—
cycle
K, K Clock Low Pulse Width
t_KLKH
0.45
—
0.45
—
0.45
—
cycle
K to K High
t_KHKH
0.45
0.55
0.45
0.55
0.45
0.55
cycle
DLL Lock Time
t_Lock
2048
—
2048
—
2048
—
cycle 4
K Static to DLL reset
t_Reset
30
—
30
—
30
—
ns
K, K Clock Initialization
Output Times
t_Init
20
—
20
—
20
—
s 5
K to CQ High
t_KHCQH
–0.45
0.45
–0.45
0.45
–0.45
0.45
ns
CQ, CQ High to Data Output Valid
t_CQHQV
—
0.15
—
0.15
—
0.15
ns
CQ, CQ High to Data Output Hold
t_CQHQX
–0.15
—
–0.15
—
–0.15
—
ns
CQ, CQ High to QLVD
t_QVLD
–0.15
0.15
–0.15
0.15
–0.15
0.15
ns
CQ to CQ High
t_CQHCQH
t_KHKH (min)
- 0.15
t_KHKH (max)
+ 0.15
t_KHKH (min)
- 0.15
t_KHKH (max)
+ 0.15
t_KHKH (min)
- 0.15
t_KHKH (max)
+ 0.15
ns
K Clock High to Data Output High-Z t_KHQZ
—
0.45
—
0.45
—
0.45
ns
K Clock High to Data Output Low-Z t_KHQX1
–0.45
—
–0.45
—
–0.45
—
ns
Input Setup & Hold Times (see Note 1)
Address Input Setup Time
t_AVKH
0.35
—
0.35
—
0.35
—
ns
Address Input Hold Time
t_KHAX
0.35
—
0.35
—
0.35
—
ns
R, W Control Input Setup Time
t_IVKH
0.35
—
0.35
—
0.35
—
ns
R, W Control Input Hold Time
t_KHIX
0.35
—
0.35
—
0.35
—
ns
BWn Control Input Setup Time
t_IVKH not specified
—
not specified
—
not specified
—
ns 2
BWn Control Input Hold Time
t_KHIX not specified
—
not specified
—
not specified
—
ns 2
BWn Control Input Pulse Width
t_IPW
0.25
—
0.25
—
0.25
—
ns
Data Input Setup Time
t_DVKH not specified
—
not specified
—
not specified
—
ns 2
Data Input Hold Time
t_KHDX not specified
—
not specified
—
not specified
—
ns 2
Data Input Pulse Width
t_DPW
0.25
—
0.25
—
0.25
—
ns
Notes:
1. All inputs must meet the specified setup and hold times at all latching clock edges.
2. The unspecified setup and hold time requirements for BWn and Data Inputs are met by the controller IP via per-pin calibration/deskew. 
Consequently, input pulse width requirements are specified for these particular signals.
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
4. V_DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V_DD and input clocks are stable.
5. After device power-up, 20s of stable input clocks (as specified by tInit) must be supplied before reads and writes are issued.
Rev: 1.01 4/2016
15/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology