GS81284Z36GB-200IV Datasheet, PDF (7/29 Pages) GSI Technology – 144Mb Pipelined and Flow Through Synchronous NBT SRAM

GS81284Z18/36B-xxxV
Pipelined and Flow Through Read Write Control State Diagram
D
B
Deselect
R
W
D
W
New Read
R
B
R
W
Burst Read
B
D
Key
Input Command Code
ƒ _Transition
Current State (n)
Next State (n+1)
n
n+1
Clock (CK)
D
R New Write
W
B
RW
Burst Write
B
D
Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
n+2
n+3
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram
Rev: 1.02 7/2010
7/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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