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GS81284Z36GB-200IV Datasheet, PDF (4/29 Pages) GSI Technology – 144Mb Pipelined and Flow Through Synchronous NBT SRAM
GS81284Z18/36B-xxxV
GS81284Z18/36B-xxxV 119-Bump BGA Pin Description
Symbol
A0, A1
An
DQA
DQB
DQC
DQD
BA, BB, BC, BD
NC
CK
CKE
W
E1
E3
E2
G
ADV
ZZ
FT
LBO
ZQ
TMS
TDI
TDO
TCK
VDD
VSS
VDDQ
Type
I
I
I/O
I
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Data Input and Output pins
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
Clock Input Signal; active high
Clock Enable; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
FLXDrive Output Impedance Control
Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
BPR1999.05.18
Rev: 1.02 7/2010
4/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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