GS81284Z36GB-200IV Datasheet, PDF (6/29 Pages) GSI Technology – 144Mb Pipelined and Flow Through Synchronous NBT SRAM

GS81284Z18/36B-xxxV
Synchronous Truth Table
Operation
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Notes
Read Cycle, Begin Burst
R
External L-H L
L HX L H LLL Q
Read Cycle, Continue Burst
B
Next
L-H L
H XX X X XLL Q
1,10
NOP/Read, Begin Burst
R
External L-H L
L H X L H L H L High-Z 2
Dummy Read, Continue Burst
B
Next
L-H L
H X X X X X H L High-Z 1,2,10
Write Cycle, Begin Burst
W
External L-H L
L LL L H LXL D
3
Write Abort, Begin Burst
D
None L-H L
L L H L H L X L High-Z 1
Write Cycle, Continue Burst
B
Next
L-H L
H X L X X X X L D 1,3,10
Write Abort, Continue Burst
B
Next
L-H L
H X H X X X X L High-Z 1,2,3,10
Deselect Cycle, Power Down
D
None L-H L
L X X H X X X L High-Z
Deselect Cycle, Power Down
D
None L-H L
L X X X X H X L High-Z
Deselect Cycle, Power Down
D
None L-H L
L X X X L X X L High-Z
Deselect Cycle, Continue
D
None L-H L
H X X X X X X L High-Z 1
Sleep Mode
None
XX
X X X X X X X H High-Z
Clock Edge Ignore, Stall
Current L-H H
X XX X X XXL
-
4
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect
cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is
sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write
cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.02 7/2010
6/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology