GS81284Z36GB-200IV Datasheet, PDF (20/29 Pages) GSI Technology – 144Mb Pipelined and Flow Through Synchronous NBT SRAM

JTAG TAP Block Diagram
GS81284Z18/36B-xxxV
····· ···
Boundary Scan Register
·
·
·
0
Bypass Register
210
Instruction Register
TDI
TDO
ID Code Register
· 31 30 29 · · · 2 1 0
Control Signals
TMS
TCK
Test Access Port (TAP) Controller
* For the value of M, see the BSDL file, which is available at by contacting us at [e-mail].
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Not Used
GSI Technology
JEDEC Vendor
ID Code
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X X X X X X X X X X X X X X X X X 0 0 011011001 1
Rev: 1.02 7/2010
20/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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