GS81284Z36GB-200IV Datasheet, PDF (1/29 Pages) GSI Technology – 144Mb Pipelined and Flow Through Synchronous NBT SRAM

GS81284Z18/36B-xxxV
119-Bump BGA
Commercial Temp
Industrial Temp
144Mb Pipelined and Flow Through
Synchronous NBT SRAM
200 MHz–167 MHz
1.8 V or 2.5 V V_DD
1.8 V or 2.5 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 8Mb, 36Mb, and 72Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-BGA package
• RoHS-compliant 119-BGA packages available
Functional Description
The GS81284Z18/36(B)-xxxV is a 144Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS81284Z18/36-xxxV may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS81284Z18/36-xxxV is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump p BGA package.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Parameter Synopsis
-200
-167
Unit
t_KQ
tCycle
3.0
3.4
ns
5.0
6.0
ns
Curr (x18)
Curr (x36)
420
385
mA
480
430
mA
t_KQ
tCycle
7.5
8.0
ns
7.5
8.0
ns
Curr (x18)
Curr (x36)
340
330
mA
370
360
mA
Rev: 1.02 7/2010
1/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology