GS78132AB Datasheet, PDF (7/12 Pages) GSI Technology – 256K x 32 8Mb Asynchronous SRAM

Address
CE
BA, BB,
BC, BD
OE
Data Out
Read Cycle 2: WE = VIH
tRC
tAA
tAC
tLZ
tAB
tBLZ
tOE
tOLZ
High impedance
tHZ
tBHZ
tOHZ
Data valid
GS78132AB
* These parameters are sampled and are not 100% tested
Write Cycle
Parameter
Write cycle time
Address valid to end of write
Chip enable to end of write
Data set up time
Data hold time
Write pulse width
Address set up time
Write recovery time (WE)
Write recovery time (CE)
Output Low Z from end of write
Write to output in High Z
-8
-10
-12
Symbol
Unit
Min Max Min Max Min Max
tWC
8
—
10
—
12
—
ns
tAW
5.5
—
7
—
8
—
ns
tCW
5.5
—
7
—
8
—
ns
tDW
4
—
5
—
6
—
ns
tDH
0
—
0
—
0
—
ns
tWP
5.5
—
7
—
8
—
ns
tAS
0
—
0
—
0
—
ns
tWR
0
—
0
—
0
—
ns
tWR1
0
—
0
—
0
—
ns
tWLZ^*
3
—
3
—
3
—
ns
tWHZ^*
—
3.5
—
4
—
5
ns
Rev: 1.04 5/2006
7/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology