GS74116A Datasheet, PDF (7/14 Pages) GSI Technology – 256K x 16 4Mb Asynchronous SRAM

Read Cycle 2: WE = V_IH
Address
CE
UB, LB
OE
Data Out
tRC
tAA
tAC
tLZ
tAB
tBLZ
tOE
tOLZ
High impedance
tHZ
tBHZ
tOHZ
Data valid
GS74116ATP/J/X
Write Cycle
Parameter
Write cycle time
Address valid to end of write
Chip enable to end of write
Byte enable to end of write
Data set up time
Data hold time
Write pulse width
Address set up time
Write recovery time (WE)
Write recovery time (CE)
Output Low Z from end of write
Write to output in High Z
-7
-8
-10
-12
Symbol
Unit
Min Max Min Max Min Max Min Max
tWC
7
—
8
—
10
—
12
—
ns
tAW
5
—
5.5
—
7
—
8
—
ns
tCW
5
—
5.5
—
7
—
8
—
ns
tBW
5
—
5.5
—
7
—
8
—
ns
tDW
3.5
—
4
—
4.5
—
6
—
ns
tDH
0
—
0
—
0
—
0
—
ns
tWP
5
—
5.5
—
7
—
8
—
ns
tAS
0
—
0
—
0
—
0
—
ns
tWR
0
—
0
—
0
—
0
—
ns
tWR1
0
—
0
—
0
—
0
—
ns
tWLZ^*
3
—
3
—
3
—
3
—
ns
tWHZ^*
—
3
—
3.5
—
4
—
5
ns
* These parameters are sampled and are not 100% tested.
Rev: 1.03 10/2002
7/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.