GS74116A Datasheet, PDF (6/14 Pages) GSI Technology – 256K x 16 4Mb Asynchronous SRAM

AC Characteristics
GS74116ATP/J/X
Read Cycle
Parameter
Read cycle time
Address access time
Chip enable access time (CE)
Byte enable access time (UB, LB)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
Output enable to output in low Z (OE)
Byte enable to output in low Z (UB, LB)
Chip disable to output in High Z (CE)
Output disable to output in High Z (OE)
Byte disable to output in High Z (UB, LB)
-7
-8
-10
-12
Symbol
Unit
Min Max Min Max Min Max Min Max
tRC
7—8
— 10 — 12 —
ns
tAA
—7—
8
— 10 — 12
ns
tAC
—7—
8
— 10 — 12
ns
tAB
— 3 — 3.5 —
4
—
5
ns
tOE
— 3 — 3.5 —
4
—
5
ns
tOH
3—3
—
3
—
3
—
ns
tLZ^*
3—3
—
3
—
3
—
ns
tOLZ^*
0—0
—
0
—
0
—
ns
tBLZ^*
0—0
—
0
—
0
— ns
tHZ^*
— 3.5 —
4
—
5
—
6
ns
tOHZ^*
—
3
— 3.5 —
4
—
5
ns
tBHZ^*
— 3 — 3.5 —
4
—
5
ns
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = V_IL, WE = V_IH, UB and, or LB = V_IL
Address
Data Out
tOH
Previous Data
tRC
tAA
Data valid
Rev: 1.03 10/2002
6/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.