GS74116A Datasheet, PDF (2/14 Pages) GSI Technology – 256K x 16 4Mb Asynchronous SRAM

Top View
TSOP-II 256K x 16 Pin Configuration (Package TP)
A4
1
A3
2
A2
3
A1
4
Top view
A0
5
CE
6
DQ1
7
DQ2
8
DQ3
9
DQ4
10
V_DD
11
44 pin
V_SS
DQ5
12
13
TSOP II
DQ6
14
DQ7
15
DQ8
16
WE
17
A15
18
A14
19
A13
20
A12
21
A16
22
44
A5
43
A6
42
A7
41
OE
40
UB
39
LB
38
DQ16
37
DQ15
36
DQ14
35
DQ13
34
33
32
V_SS
V_DD
DQ12
31
DQ11
30
DQ10
29
DQ9
28
NC
27
A8
26
A9
25
A10
24
A11
23
A17
Block Diagram
A0
Row
Decoder
Address
Input
Buffer
A17
CE
WE
OE
Control
UB ^_____
LB ^_____
Memory Array
Column
Decoder
I/O Buffer
DQ1 DQ16
GS74116ATP/J/X
Rev: 1.03 10/2002
2/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.