GS8180QV18D Datasheet, PDF (6/32 Pages) GSI Technology – 18Mb Burst of 2 SigmaQuad SRAM

GS8180QV18/36D-200/167/133/100*
Burst of 2 SigmaQuad SRAM DDR Write
The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of
K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is
clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on
the rising edge of K along with the write address. A high on W causes a write port deselect cycle.
Write A
Burst of 2 Double Data Rate SigmaQuad SRAM Write First
Read B
Read C Write D NOP
Read E Write F Read G Write H NOP
K
Kbar
Address
Rbar
Wbar
BWx bar
D
C
Cbar
Q
A
B
C
D
E
F
G
H
A
A+1
D
D+1
F
F+1
H
H+1
B
B+1
C
C+1
E
E+1
G
Special Functions
Byte Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Rev: 2.03 10/2004
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology