GS8180QV18D Datasheet, PDF (5/32 Pages) GSI Technology – 18Mb Burst of 2 SigmaQuad SRAM

GS8180QV18/36D-200/167/133/100*
interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and disadvantages. The
user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application at
hand.
Alternating Read-Write Operations
SigmaQuad SRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted and re-started.
- R and W high always deselects the RAM.
- All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for
details.
Burst of 2 SigmaQuad SRAM DDR Read
The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R,
begins a read cycle. Data can be clocked out one cycle later and again one half cycle after that. A high on the Read Enable-bar pin,
R, begins a read port deselect cycle.
Read A
Burst of 2 Double Data Rate SigmaQuad SRAM Read First
NOP
Write B
Read C Write D Read E Write F Read G Write H NOP
K
Kbar
Address
A
Rbar
Wbar
BWx bar
D
C
Cbar
Q
B
C
D
E
F
G
H
B
B+1
D
D+1
F
F+1
H
H+1
A
A+1
C
C+1
E
E+1
G
Rev: 2.03 10/2004
5/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology