GS8180QV18D Datasheet, PDF (4/32 Pages) GSI Technology – 18Mb Burst of 2 SigmaQuad SRAM

GS8180QV18/36D-200/167/133/100*
Pin Description Table
Symbol
Description
SA
Synchronous Address Inputs
NC
No Connect
R
Synchronous Read
W
Synchronous Write
BW0–BW1
Synchronous Byte Writes
K
Input Clock
K
Input Clock
C
Output Clock
C
Output Clock
TMS
Test Mode Select
TDI
Test Data Input
TCK
Test Clock Input
TDO
Test Data Output
V_REF
HSTL Input Reference Voltage
ZQ
Output Impedance Matching Input
MCL
Must Connect Low
D0–D17
Synchronous Data Inputs
Q0–Q17
Synchronous Data Outputs
V_DD
Power Supply
V_DDQ
Isolated Output Buffer Supply
V_SS
Power Supply: Ground
Note:
NC = Not Connected to die or any other pin
Type
Input
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
—
Input
Output
Supply
Supply
Supply
Comments
—
—
Active Low
Active Low
Active Low
Active High
Active Low
Active High
Active Low
—
—
—
—
—
—
—
2.5 V Nominal
1.8 or 1.5 V Nominal
—
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
A SigmaQuad SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate
I/O SRAM that shares a common address between its two ports to keep both ports running all the time, the RAM must implement
some sort of burst transfer protocol. The burst must be at least long enough to cover the time the opposite port is receiving
instructions on what to do next. The rate at which a RAM can accept a new random address is the most fundamental performance
metric for the RAM. Each of the three SigmaQuad SRAMs support similar address rates because random address rate is
determined by the internal performance of the RAM and they are all based on the same internal circuits. Differences between the
truth tables of the different SigmaQuad SRAMs, or any other Separate I/O SRAMs, follow from differences in how the RAM’s
Rev: 2.03 10/2004
4/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology