GS8170LW36AC Datasheet, PDF (6/32 Pages) GSI Technology – 18Mb Σ1x1Lp CMOS I/O Late Write SigmaRAM

GS8170LW36/72AC-350/333/300/250
Late Write
In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late
Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT
SRAMs.
SigmaRAM Late Write with Pipelined Read
Read
Deselect
W rite
Read
Read
CK
Address
A
XX
C
D
E
F
ADV
/E1
/W
DQ
QA
DC
QD
CQ
Key
Hi-Z
Access
Byte Write Control
The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,
including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle.
Example of x36 Byte Write Truth Table
Function
Read
Write Byte A
Write Byte B
Write Byte C
Write Byte D
Write all Bytes
Write Abort
W
Ba
Bb
Bc
Bd
H
X
X
X
X
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
H
H
Rev: 1.04 4/2005
6/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology