GS8170LW36AC Datasheet, PDF (12/32 Pages) GSI Technology – 18Mb Σ1x1Lp CMOS I/O Late Write SigmaRAM

.
CK
Address
ADV
/E1
/E2 Bank 1
E2 Bank 2
DQ
Bank 1
CQ
Bank 1
Read
A
GS8170LW36/72AC-350/333/300/250
Pipelined Read Bank Switch with E1 Deselect
No Op
Read
Read
Read
XX
C
D
E
F
QA
CQ1 + CQ2
CQ
Bank 2
DQ
Bank 2
QC
QD
Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
CMOS Output Driver Impedance Control
CMOS I/O SigmaRAMs are supplied with selectable (high or low) impedance output drivers. The ZQ pin allows selection between
SRAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ high) point-to-point
applications.
Rev: 1.04 4/2005
12/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology