GS8170LW36AC Datasheet, PDF (10/32 Pages) GSI Technology – 18Mb Σ1x1Lp CMOS I/O Late Write SigmaRAM

GS8170LW36/72AC-350/333/300/250
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the
Echo Clocks.
Programmable Enables
ΣRAMs feature two user-programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active
low or active high inputs, is determined by the state of the programming inputs, EP2 and EP3. For example, if EP2 is held at V_DD,
E2 functions as an active high enable. If EP2 is held to V_SS, E2 functions as an active low chip enable input.
Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming
the enable inputs of four SRAMs in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four
SRAMs can be made to look like one larger RAM to the system.
Example Four Bank Depth Expansion Schematic—Σ1x1Lp
A₀–A_n
E1
CK
W
DQ₀–DQ_n
A₀–A_{n – 2}
A_{n – 1}
A_n
CQ
Bank 0
A
A₀–A_{n – 2}
E3
A_{n – 1}
E2
A_n
E1
CK
W ^{EP3 0}
DQ EP2 ₀
CQ
Bank 1
A
A₀–A_{n – 2}
E3
A_{n – 1}
E2
A_n
E1
CK
W ^{EP3 1}
DQ EP2 0
CQ
Bank Enable Truth Table
Bank 2
A
E3
E2
A₀–A_{n – 2}
A_{n – 1}
A_n
E1
CK
W ^{EP3 0}
DQ EP2 ₁
CQ
Bank 3
A
E3
E2
E1
CK
W ^{EP3 1}
DQ EP2 1
CQ
EP2
Bank 0
V_SS
Bank 1
V_SS
Bank 2
V_DD
Bank 3
V_DD
EP3
E2
E3
V_SS
Active Low Active Low
V_DD
Active Low Active High
V_SS
Active High Active Low
V_DD
Active High Active High
Rev: 1.04 4/2005
10/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology