GS81302T18GE-333I Datasheet, PDF (6/36 Pages) GSI Technology – 144Mb SigmaDDRTM-II Burst of 2 SRAM

GS81302T08/09/18/36E-375/350/333/300/250
Pin Description Table
Symbol
Description
Type
Comments
SA
Synchronous Address Inputs
Input
—
R/W
Synchronous Read/Write
Input
Read: Active High
Write: Active Low
BW0–BW3
Synchronous Byte Writes
Input
Active Low
x18/x36 only
NW0–NW1
Nybble Write Control Pin
Input
Active Low
x8 only
LD
Synchronous Load Pin
Input
Active Low
K
Input Clock
Input
Active High
K
Input Clock
Input
Active Low
C
Output Clock
Input
Active High
C
Output Clock
Input
Active Low
TMS
Test Mode Select
Input
—
TDI
Test Data Input
Input
—
TCK
Test Clock Input
Input
—
TDO
Test Data Output
Output
—
V_REF
HSTL Input Reference Voltage
Input
—
ZQ
Output Impedance Matching Input
Input
—
MCL
Must Connect Low
—
—
DQ
Data I/O
Input/Output
Three State
Doff
Disable DLL when low
Input
Active Low
CQ
Output Echo Clock
Output
—
CQ
Output Echo Clock
Output
—
V_DD
Power Supply
Supply
1.8 V Nominal
V_DDQ
Isolated Output Buffer Supply
Supply
1.8 V or 1.5 V Nominal
V_SS
Power Supply: Ground
Supply
—
NC
No Connect
—
—
Notes:
1. NC = Not Connected to die or any other pin
2. C, C, K, K cannot be set to V_REF voltage.
3. When ZQ pin is directly connected to V_DDQ, output impedance is set to minimum and it cannot be connected to ground or left unconnected.
Rev: 1.03b 12/2011
6/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology