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GS81302T18GE-333I Datasheet, PDF (14/36 Pages) GSI Technology – 144Mb SigmaDDRTM-II Burst of 2 SRAM
GS81302T08/09/18/36E-375/350/333/300/250
Thermal Impedance
Package
Test PCB
Substrate
θ JA (C°/W)
Airflow = 0 m/s
θ JA (C°/W)
Airflow = 1 m/s
θ JA (C°/W)
Airflow = 2 m/s
θ JB (C°/W) θ JC (C°/W)
165 BGA
4-layer
16.4
13.4
12.4
8.6
1.2
Notes:
1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
HSTL I/O DC Input Characteristics
Parameter
Symbol
Min
Max
Units
Notes
DC Input Logic High
VIH (dc)
VREF + 0.10
VDDQ + 0.3 V
V
1
DC Input Logic Low
VIL (dc)
–0.3 V
VREF – 0.10
V
1
Notes:
1. Compatible with both 1.8 V and 1.5 V I/O drivers
2. These are DC test criteria. DC design criteria is VREF ± 50 mV. The AC VIH/VIL levels are defined separately for measuring timing parame-
ters.
3. VIL (Min) DC = –0.3 V, VIL(Min) AC = –1.5 V (pulse width ≤ 3 ns).
4. VIH (Max) DC = VDDQ + 0.3 V, VIH(Max) AC = VDDQ + 0.85 V (pulse width ≤ 3 ns).
HSTL I/O AC Input Characteristics
Parameter
Symbol
Min
Max
Units
AC Input Logic High
VIH (ac)
VREF + 0.20
—
V
AC Input Logic Low
VIL (ac)
—
VREF – 0.20
V
VREF Peak-to-Peak AC Voltage
VREF (ac)
—
5% VREF (DC)
V
Notes:
1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other.
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
Notes
2,3
2,3
1
Rev: 1.03b 12/2011
14/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology