GS81302T18GE-333I Datasheet, PDF (11/36 Pages) GSI Technology – 144Mb SigmaDDRTM-II Burst of 2 SRAM

GS81302T08/09/18/36E-375/350/333/300/250
Burst of 2 Byte Write Clock Truth Table
BW
BW
Current Operation
K↑
(t_{n + 1})
T
K↑
(t_{n + 1½})
T
K↑
(t_n)
Write
Dx stored if BWn = 0 in both data transfers
T
F
Write
Dx stored if BWn = 0 in 1st data transfer only
F
T
Write
Dx stored if BWn = 0 in 2nd data transfer only
F
F
Write Abort
No Dx stored in either data transfer
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
Burst of 2 Nybble Write Clock Truth Table
NW
NW
Current Operation
K↑
(t_{n + 1})
T
K↑
(t_{n + 1½})
T
K↑
(t_n)
Write
Dx stored if NWn = 0 in both data transfers
T
F
Write
Dx stored if NWn = 0 in 1st data transfer only
F
T
Write
Dx stored if NWn = 0 in 2nd data transfer only
F
F
Write Abort
No Dx stored in either data transfer
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
D
K↑
(t_{n + 1})
D1
D1
X
X
D
K↑
(t_{n + 1½})
D2
X
D2
X
D
K↑
(t_{n + 1})
D1
D1
X
X
D
K↑
(t_{n + 1½})
D2
X
D2
X
Rev: 1.03b 12/2011
11/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology