GS81302S08 Datasheet, PDF (6/35 Pages) GSI Technology – 144Mb SigmaSIOTM DDR -II Burst of 2 SRAM

GS81302S08/09/18/36E-375/350/333/300/250
Pin Description Table
Symbol
Description
Type
Comments
SA
Synchronous Address Inputs
Input
—
R/W
Read/Write Contol Pin
Input
Write Active Low; Read Active High
NW0–NW1
Synchronous Nybble Writes
Input
Active Low
x08 Version
BW0–BW1
Synchronous Byte Writes
Input
Active Low
x18 Version
BW0–BW3
Synchronous Byte Writes
Input
Active Low
x36 Version
K
Input Clock
Input
Active High
C
Output Clock
Input
Active High
TMS
Test Mode Select
Input
—
TDI
Test Data Input
Input
—
TCK
Test Clock Input
Input
—
TDO
Test Data Output
Output
—
V_REF
HSTL Input Reference Voltage
Input
—
ZQ
Output Impedance Matching Input
Input
—
K
Input Clock
Input
Active Low
C
Output Clock
Output
Active Low
D_OFF
DLL Disable
—
Active Low
LD
Synchronous Load Pin
—
Active Low
CQ
Output Echo Clock
Output
Active Low
CQ
Output Echo Clock
Output
Active High
Dn
Synchronous Data Inputs
Input
—
Qn
Synchronous Data Outputs
Output
—
V_DD
Power Supply
Supply
1.8 V Nominal
V_DDQ
Isolated Output Buffer Supply
Supply
1.8 or 1.5 V Nominal
V_SS
Power Supply: Ground
Supply
—
NC
No Connect
—
—
Notes:
1. C, C, K, or K cannot be set to V_REF voltage.
2. When ZQ pin is directly connected to V_DDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. NC = Not Connected to die or any other pin
Rev: 1.03b 12/2011
6/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology