GS81302S08 Datasheet, PDF (11/35 Pages) GSI Technology – 144Mb SigmaSIOTM DDR -II Burst of 2 SRAM

GS81302S08/09/18/36E-375/350/333/300/250
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaSIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected
to V_SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching
with a vendor-specified tolerance is between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as
the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for
drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts
again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The
output driver is implemented with discrete binary weighted impedance steps.
Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table
A
LD
R/W
Current
Operation
D
D
K↑
K↑
K↑
K↑
(t_n)
(t_n)
(t_n)
(t_n)
K↑
(t_{n + 1})
K↑
(t_{n + 1½})
X
1
X
Deselect
X
X
V
0
1
Read
X
X
V
0
0
Write
D0
D1
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations.
3. D0 and D1 indicate the first and second pieces of input data transferred during Write operations.
4. Users should not clock in metastable addresses.
Q
K↑
(t_{n + 1½})
Hi-Z
Q0
Hi-Z
Q
K↑
(t_{n + 2})
Hi-Z
Q1
Hi-Z
Rev: 1.03b 12/2011
11/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology