|
GS81302S08 Datasheet, PDF (1/35 Pages) GSI Technology – 144Mb SigmaSIOTM DDR -II Burst of 2 SRAM | |||
|
GS81302S08/09/18/36E-375/350/333/300/250
165-Bump BGA
Commercial Temp
Industrial Temp
144Mb SigmaSIOTM DDR -II
Burst of 2 SRAM
375 MHzâ250 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
⢠Simultaneous Read and Write SigmaSIO⢠Interface
⢠JEDEC-standard pinout and package
⢠Dual Double Data Rate interface
⢠Byte Write controls sampled at data-in time
⢠DLL circuitry for wide output data valid window and future
frequency scaling
⢠Burst of 2 Read and Write
⢠1.8 V +100/â100 mV core power supply
⢠1.5 V or 1.8 V HSTL Interface
⢠Pipelined read operation
⢠Fully coherent read and write pipelines
⢠ZQ mode pin for programmable output drive strength
⢠IEEE 1149.1 JTAG-compliant Boundary Scan
⢠165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
⢠RoHS-compliant 165-bump BGA package available
SigmaSIO⢠Family Overview
GS81302S08/09/18/36 are built in compliance with the
SigmaSIO DDR-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous
device. It employs dual input register clock inputs, K and K.
The device also allows the user to manipulate the output
register clock input quasi independently with dual output
register clock inputs, C and C. If the C clocks are tied high, the
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
K clocks are routed internally to fire the output registers
instead. Each Burst of 2 SigmaSIO DDR-II SRAM also
supplies Echo Clock outputs, CQ and CQ, which are
synchronized with read data output. When used in a source
synchronous clocking scheme, the Echo Clock outputs can be
used to fire input registers at the dataâs destination.
Each internal read and write operation in a SigmaSIO DDR-II
B2 RAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaSIO DDR-II B2 is always one address pin less
than the advertised index depth (e.g., the 16M x 8 has an 8M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-375
2.66 ns
0.45 ns
-350
2.86 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
Rev: 1.03b 12/2011
1/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
|
▷ |