GS8182D18D Datasheet, PDF (5/27 Pages) GSI Technology – 18Mb Burst of 4 SigmaQuad-II SRAM

Preliminary
GS8182D18D-250/200/167
SigmaQuad-II B4 SRAM DDR Read
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on
the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Data
can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), after the following
rising edge of K with a rising edge of C (or by K if C and C are tied high), after the next rising edge of K with a rising edge of C,
and after the following rising edge of K with a rising edge of C. Clocking in a high on the Read Enable-bar pin, R, begins a read
port deselect cycle.
Burst of 4 Double Data Rate SigmaQuad-II SRAM Read First
Read A
NOP
Read B
Write C
Read D
Write E
NOP
K
K
Address
A
R
W
BWx
D
C
C
Q
CQ
CQ
B
C
D
E
C
C+1
C+2
C+3
E
E+1
A
A+1
A+2
A+3
B
B+1
B+2
B+3
D
D+1
D+2
Rev: 1.02 11/2004
5/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology