GS8182D18D Datasheet, PDF (24/27 Pages) GSI Technology – 18Mb Burst of 4 SigmaQuad-II SRAM

Preliminary
GS8182D18D-250/200/167
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
1.8 V Test Port Input High Voltage
1.8 V Test Port Input Low Voltage
V_IHJ
0.6 * V_DD
V_ILJ
–0.3
V_DD +0.3
0.3 * V_DD
V
1
V
1
TMS, TCK and TDI Input Leakage Current
I_INHJ
–300
1
uA
2
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
I_INLJ
–1
I_OLJ
–1
V_OHJ
1.7
V_OLJ
—
100
uA
3
1
uA
4
—
V 5, 6
0.4
V 5, 7
Test Port Output CMOS High
V_OHJC V_DDQ – 100 mV
—
V 5, 8
Test Port Output CMOS Low
V_OLJC
—
100 mV
V 5, 9
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < V_DDn +2 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.
2. V_ILJ ≤ V_IN ≤ V_DDn
3. 0 V ≤ V_IN ≤ V_ILJn
4. Output Disable, V_OUT = 0 to V_DDn
5. The TDO output driver is served by the V_DDQ supply.
6. I_OHJ = –4 mA
7. I_OLJ = + 4 mA
8. I_OHJC = –100 uA
9. I_OHJC = +100 uA
JTAG Port AC Test Conditions
Parameter
Symbol
Min
Unit
Input High/Low Level
V_IH/V_IL
1.3/0.5
V
Input Rise/Fall Time
TR/TF
1.0/1.0
ns
Input and Output Timing Reference Level
0.9
V
Notes:
1. Distributed scope and test jig capacitance.
2. Test conditions as shown unless otherwise noted.
Rev: 1.02 11/2004
24/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology