GS8182D18D Datasheet, PDF (10/27 Pages) GSI Technology – 18Mb Burst of 4 SigmaQuad-II SRAM

Preliminary
GS8182D18D-250/200/167
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
V_SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching
with a vendor-specified tolerance is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as
the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for
drifts in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation,
resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the
optimum level. The output driver is implemented with discrete binary weighted impedance steps.
x18 Byte Write Enable (BWn) Truth Table
BW0 BW1
1
1
0
1
1
0
0
0
D0–D8
Don’t Care
Data In
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
Data In
Rev: 1.02 11/2004
10/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology