GS71208TP Datasheet, PDF (5/11 Pages) GSI Technology – 128K x 8 1Mb Asynchronous SRAM

AC Test Conditions
Parameter
Input high level
Input low level
Input rise time
Input fall time
Input reference level
Output reference level
Output load
Conditions
VIH = 2.4 V
VIL = 0.4 V
tr = 1 V/ns
tf = 1 V/ns
1.4 V
1.4 V
Fig. 1& 2
Note:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
AC Characteristics
Read Cycle
Parameter
Read cycle time
Address access time
Chip enable access time (CE)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
Output enable to output in low Z (OE)
Chip disable to output in High Z (CE)
Output disable to output in High Z (OE)
* These parameters are sampled and are not 100% tested
GS71208TP
Output Load 1
DQ
50Ω 30pF¹
VT = 1.4 V
Output Load 2
3.3 V
DQ
589Ω
5pF^{1 434Ω}
Symbol
tRC
tAA
tAC
tOE
tOH
tLZ^*
tOLZ^*
tHZ^*
tOHZ^*
-8
Unit
Min
Max
8
—
ns
—
8
ns
—
8
ns
—
3.5
ns
3
—
ns
3
—
ns
0
—
ns
—
4
ns
—
3.5
ns
Rev: 1.03 10/2001
5/11
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.