GS71208TP Datasheet, PDF (2/11 Pages) GSI Technology – 128K x 8 1Mb Asynchronous SRAM

Block Diagram
Truth Table
CE
OE
H
X
L
L
L
X
L
H
Note: X: “H” or “L”
A0
Row
Decoder
Address
Input
Buffer
A16
CE
WE
OE
Control
Memory Array
Column
Decoder
I/O Buffer
DQ1
DQ8
WE
DQ1 to DQ8
X
Not Selected
H
Read
L
Write
H
High Z
GS71208TP
V_DD Current
ISB1, ISB2
IDD
Rev: 1.03 10/2001
2/11
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.