GS81314PT18 Datasheet, PDF (4/40 Pages) GSI Technology – 144Mb SigmaDDR-IVe™ Burst of 2 Single-Bank ECCRAM™

GS81314PT18/36GK-133/120/106
Pin Description
Symbol
Description
SA[21:0]
DQ[35:0]
DQINV[3:0]
QVLD[1:0]
CK, CK
KD[1:0],
KD[1:0]
CQ[1:0],
CQ[1:0]
LD
R/W
MRW
PLL
RST
ZQ
RCS
Address — Read or write address is registered on CK.
Write/Read Data — Registered on KD and KD during Write operations; aligned with CQ and CQ
during Read operations.
DQ[17:0] - x18 and x36.
DQ[35:18] - x36 only.
Write/Read Data Inversion — Registered on KD and KD (along with write data) during Write operations;
indicate if the associated write data byte is inverted (DQINVx = 1) or not (DQINVx = 0). Aligned with CQ
and CQ (along with read data) during Read operations; indicate if the associated read data byte is inverted
(DQINVx = 1) or not (DQINVx = 0).
DQINV0 - associated with DQ[8:0] in x18 and x36.
DQINV1 - associated with DQ[17:9] in x18 and x36.
DQINV2 - associated with DQ[26:18] in x36 only.
DQINV3 - associated with DQ[35:27] in x36 only.
Note: Treated as NU I/Os when Data Inversion is disabled.
Read Data Valid — Driven high one half cycle before valid read data.
Primary Input Clocks — Dual single-ended. Used for latching address and control inputs, for internal timing
control, and for output timing control.
Write Data Input Clocks — Dual single-ended. Used for latching write data inputs.
KD0, KD0: latch DQ[17:0], DQINV[1:0] in x36, and DQ[8:0], DQINV0 in x18.
KD1, KD1: latch DQ[35:18], DQINV[3:2] in x36, and DQ[17:9], DQINV1 in x18.
Read Data Output Clocks — Free-running output (echo) clocks, tightly aligned with read data outputs.
Facilitate source-synchronous operation.
CQ0, CQ0: align with DQ[17:0], DQINV[1:0] in x36, and DQ[8:0], DQINV0 in x18.
CQ1, CQ1: align with DQ[35:18], DQINV[3:2] in x36, and DQ[17:9], DQINV1 in x18.
Load Enable — Registered onCK. See the Clock Truth Table for functionality.
Read / Write Enable — Registered on CK. See the Clock Truth Table for functionality.
Mode Register Write — Registered onCK. Can be used synchronously or asynchronously to enable Reg-
ister Write Mode. See the State and Clock Truth Tables for functionality.
PLL Enable — Weakly pulled High internally.
PLL = 0: disables internal PLL.
PLL = 1: enables internal PLL.
Reset — Holds the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
Driver / ODT Impedance Control Resistor Input — Must be connected to V_SS through an external resistor
RQ to program driver and ODT impedances.
Current Source Resistor Input — Must be connected to V_SS through an external 2K resistor to provide
an accurate current source for the PLL.
Type
Input
I/O
I/O
Output
Input
Input
Output
Input
Input
Input
Input
Input
Input
Input
Rev: 1.09 5/2016
4/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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