GS81314PT18 Datasheet, PDF (22/40 Pages) GSI Technology – 144Mb SigmaDDR-IVe™ Burst of 2 Single-Bank ECCRAM™

GS81314PT18/36GK-133/120/106
DQ ODT Control
Note: References to “DQ” in this section refer to DQ pins, and to DQINV pins when Data Inversion is enabled.
Because the POD I/O standard employs high-side (pull-up) termination only, the methodology for controlling when DQ ODT is en-
abled and disabled during Write-to-Read and Read-to-Write transitions is simply:
• The SRAM keeps its DQ termination enabled at all times except when driving read data.
• The controller keeps its DQ termination enabled at all times except when driving write data.
NOP Requirements
The number of NOPs needed during Write -> Read and Read -> Write transitions vary with Read Latency (RL) as follows:
Write -> Read Transition
min
typ
0
0
Read -> Write Transition
min
typ
RL + 1
RL + 2~5
Notes:
1. Min NOP between Write and Read (0) ensures that the SRAM disables DQ termination and begins driving the first piece of read
data RL + 0.5 cycles after it latches the last piece of write data. Typ NOP is the same as Min NOP because it is sufficient to ensure
that the controller stops driving the last piece of write data before SRAM DQ termination disable reaches it, regardless of SRAM
tKQ, prop delay between SRAM and controller, and operating frequency.
2. Min NOP between Read and Write (RL + 1) ensures that the SRAM stops driving the last piece of read data and enables DQ
termination 1 cycle before it latches the first piece of write data. Typ NOP is greater than Min NOP in order to ensure that the
controller begins driving the first piece of write data after SRAM DQ termination enable reaches it, accounting for SRAM tKQ,
prop delay between SRAM and controller, and operating frequency.
DQ ODT Control Timing Diagram (RL = 6)
Write1 Read1 NOP1 NOP2 NOP3 NOP4 NOP5 NOP6 NOP7 NOP8 NOP9 NOP10 Write1
CK, KD
SA A1
A2
A3
A4
LD
R/W
DQ D11 D12
t_KHQV
Q21 Q22
D31 D32
CQ
Note: In the diagram above, the controller is enabling its DQ ODT except when driving write data. And, the SRAM is enabling its
DQ ODT except when driving read data.
Rev: 1.09 5/2016
22/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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