GS81314PT18 Datasheet, PDF (18/40 Pages) GSI Technology – 144Mb SigmaDDR-IVe™ Burst of 2 Single-Bank ECCRAM™

GS81314PT18/36GK-133/120/106
Loopback Mode Input Group Definition and Input-to-Output Pin Mapping
Inputs are divided into 2 groups because there are up to 28 inputs to train (22 address, 2 control, and 4 KD clocks), but as few as 18
outputs available to loop them back to (in x18 devices).
There are 20 inputs per group - one per DQ, DQINV output in x18 devices, and one per two DQ, DQINV outputs in x36 devices.
Input Pins
Input Signals
Output Pins
Bit #
GP1
GP2
GP1
GP2
x18
x36
Output Signals
x18
x36
1
8T
---
SA2
RSVD
n/a
12Y
n/a
DQINV1
2
8P
8V
SA4
SA0
13V
13V, 12W
DQ8
DQ8, DQ17
3
8M
8T
SA6
SA2
13T
13T, 12U
DQ7
DQ7, DQ16
4
8J
---
SA8
RSVD
13P
13P, 12R
DQ6
DQ6, DQ15
5
9H
9L
SA16
KD0
13N
13N, 12P
DQ5
DQ5, DQ14
6
8G
9K
SA10
KD0
12J
12J, 12M
DQ4
DQ4, DQ13
7
9F
7H
SA18
R/W
12G
12G, 13H
DQ3
DQ3, DQ12
8
8E
---
SA12
RSVD
12F
12F, 13G
DQ2
DQ2, DQ11
9
9D
---
SA20
RSVD
12D
12D, 13E
DQ1
DQ1, DQ10
10
8C
---
SA14
RSVD
12B
12B, 13C
DQ0
DQ0, DQ9
20
6C
---
SA13
RSVD
12A
12A
DQINV0
DQINV0
1
8T
---
SA2
RSVD
2Y
2Y
DQINV1
DQINV2
11
6T
---
SA1
RSVD
2W
2W, 1V
DQ9
DQ18, DQ27
12
6P
6V
SA3
SA21
2U
2U, 1T
DQ10 DQ19, DQ28
13
6M
---
SA5
RSVD
2R
2R, 1P
DQ11 DQ20, DQ29
14
6J
7N
SA7
LD
2P
2P, 1N
DQ12 DQ21, DQ30
15
5H
5L
SA15
KD1
2M
2M, 2J
DQ13 DQ22, DQ31
16
6G
5K
SA9
KD1
1H
1H, 2G
DQ14 DQ23, DQ32
17
5F
---
SA17
RSVD
1G
1G, 2F
DQ15 DQ24, DQ33
18
6E
---
SA11
RSVD
1E
1E, 2D
DQ16 DQ25, DQ34
19
5D
6C
SA19
SA13
1C
1C, 2B
DQ17 DQ26, DQ35
20
6C
---
SA13
RSVD
n/a
2A
n/a
DQINV3
Notes:
1. Blue shading indicates input pins that are unused (NU) in certain device configurations. During Loopback Mode, the associated
output pins loop back the states of those input pins regardless whether they are used or unused.
2. Gray shading indicates Group 2 inputs that are reserved (RSVD) for future use. During Loopback Mode, the associated output
pins act as if they were looping back input pins tied Low.
3. Green shading indicates DQINV output pins that are unused (NU) when Data Inversion is disabled. During Loopback Mode, they
loop back the states of the associated input pins regardless whether Data Inversion is enabled or disabled.
4. The 18 unused DQ and the 2 unused DQINV in x18 devices remain in their “NU” states during Loopback Mode.
5. Bit #1 and bit #20 are repeated in the table to show that they are used in both the right and left side data bytes in x36 devices.
Rev: 1.09 5/2016
18/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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