GS816018 Datasheet, PDF (21/28 Pages) GSI Technology – 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

Pipelined SCD Read Cycle Timing
Preliminary
GS816018/32/36T-250/225/200/166/150/133
CK
ADSP
ADSC
ADV
A0–An
GW
BW
BWA–BWD
E1
E2
E3
G
DQA–DQD
Single Read
tS ^tH
Burst Read
tKH ^tKL
tKC
ADSP is blocked by E inactive
tS tH
ADSC initiated read
tS tH
Suspend Burst
tS tH
RD1
tS
RD2
RD3
tH
tS
tH
tS tH
tS tH
tS _tH
E1 masks ADSP
E2 and E3 only sampled with ADSP or ADSC
tOE
tOHZ
tOLZ
tKQX
Hi-Z
Q1A
Q2A Q2B
Q2c
tLZ
tKQ
Deselected with E2
tKQX
Q2D
Q3A
tHZ
Rev: 2.12 3/2002
21/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.