GS816018 Datasheet, PDF (20/28 Pages) GSI Technology – 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

Preliminary
GS816018/32/36T-250/225/200/166/150/133
Flow Through Read-Write Cycle Timing
Single Read
Single Write
Burst Read
CK
ADSP
tS tH
tKC
tKH tKL
ADSP is blocked by E inactive
tS tH _{ADSC initiated read}
ADSC
tS tH
ADV
tS _tH
A0–An
RD1
WR1
RD2
tS tH
GW
tS
tS tH
BW
BA–BD
E1
E2
E3
tS tH
tS tH
WR1
E1 masks ADSP
tS tH
E2 and E3 only sampled with ADSP and ADSC
tS tH
Deselected with E3
tOE tOHZ
G
DQA–DQD
tKQ
Hi-Z
Q1A
tS tH
D1A
Q2A
Q2B
Q2c Q2D ^Q2A
Burst wrap around to it’s initial state
Rev: 2.12 3/2002
20/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.