GS6150 Datasheet, PDF (31/64 Pages) Gennum Corporation – Automatic or Manual Rate Selection

Multiple chains of GS6150 devices can share a single SDOUT bus connection to host by
configuring the devices for Bus-Through operation. In such configuration, each chain
requires a separate Chip Select (CS).
SDIN pin
Configuration and
Status Register
GSPI_LINK
_DISABLE
BUS_THROUGH
SDOUT pin
High-Z
CS pin
Figure 4-7: GSPI_BUS_THROUGH_ENABLE Operation
4.11.4 SCLK Pin
The SCLK pin is the GSPI serial data shift clock input to the device, and must be provided
by the host processor.
Serial data is clocked into the GS6150 SDIN pin on the rising edge of SCLK. Serial data is
clocked out of the device from the SDOUT pin on the falling edge of SCLK (read
operation). SCLK is ignored when CS is HIGH.
The maximum interface clock rate is 27MHz.
4.11.5 Command Word Description
All GSPI accesses are a minimum of 32 bits in length (a 16-bit Command Word followed
by a 16-bit Data Word) and the start of each access is indicated by the high-to-low
transition of the chip select (CS) pin of the GS6150.
The format of the Command Word and Data Words are shown in Figure 4-8.
Data received immediately following this high-to-low transition will be interpreted as a
new Command Word.
4.11.5.1 R/W bit - B15 Command Word
This bit indicates a read or write operation.
When R/W is set to 1, a read operation is indicated, and data is read from the register
specified by the ADDRESS field of the Command Word.
When R/W is set to 0, a write operation is indicated, and data is written to the register
specified by the ADDRESS field of the Command Word.
GS6150
Final Data Sheet
PDS-060127
Rev.2
March 2015
www.semtech.com
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