GS6150 Datasheet, PDF (22/64 Pages) Gennum Corporation – Automatic or Manual Rate Selection

4.3.2.1 Synchronous and Asynchronous Lock Time
Asynchronous lock time is defined as the time it takes the device to lock when a signal
is first applied to the serial digital inputs, or when the signal rate changes.
The synchronous lock time is defined as the time it takes the device to lock to a signal
which has been momentarily interrupted.
The asynchronous and synchronous lock times are defined in Table 2-3: AC Electrical
Characteristics.
To qualify for synchronous lock time, the maximum interruption time of the signal is
10μs for a 270Mb/s signal. 1.485Gb/s, 2.97Gb/s, and 5.94Gb/s signals, as well as their
f/1.001 components have a maximum interruption time of 6μs. The new signal, after
interruption, must have the same frequency as the original signal but can have arbitrary
phase.
4.3.3 Rate Detection
The GS6150 can be manually forced to lock to a specific supported data rate, or
automatically search for and lock to supported rates. The selection between manual and
automatic rate selection is through the FORCE_PLL_RATE and
FORCE_PLL_RATE_ENABLE bits of the PLL_CONTROL register at address 4C_h. By default
the device is set to automatically search for supported SDI rates.
When set to automatically detect supported data rates, the device repeatedly cycles
through each supported rate that is enabled through the RATE_ENABLE_5G94,
RATE_ENABLE_2G97, RATE_ENABLE_1G485, RATE_ENABLE_270M and
RATE_ENABLE_125M bits of the PLL_CONTROL register, until the device phase locks to
one of the enabled rates. If lock is lost the rate search resumes, continuously testing for
each rate in sequence until lock is regained.
The device reports the current data rate setting of the automatic rate search
state machine through the DETECTED_RATE bits in the PLL_STATUS register at address
4F_h. Each bit of DETECTED_RATE is also available to output through the GPIO pins,
selected for output using the GPIO[3:0]_IO_SELECT and GPIO[3:0]_SELECT bits
accessible in the GPIO_CONTROL_REG_0 register. The supported rates that the
DETECTED_RATE bits can output are shown in Table 4-2 below.
Table 4-2: Automatic Rate Detection - Supported Data Rates
DETECTED_RATE
000
001
010
011
100
Data Rate
125Mb/s – MADI
270Mb/s – SD
1.485Gb/s – HD
2.97Gb/s – 3G
5.94Gb/s – 6G
GS6150
Final Data Sheet
PDS-060127
Rev.2
March 2015
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