GS6150 Datasheet, PDF (21/64 Pages) Gennum Corporation – Automatic or Manual Rate Selection

60
55
SD-SDI
50
HD-SDI
45
3G-SDI
40
6G-SDI
35
30
0
1.485
2.97
4.455
5.94
Frequency (Gb/s)
Figure 4-2: LOS Threshold at 100mV Input Swing vs. SDI Data Rates for a Nominal
DEVICE_SPECIFIC_LOS_THRESHOLD of 53
Strength detection is unaffected by the Trace EQ settings in INPUT_CONTROL_REG_0.
When edge detection is used as the method of LOS detection the corresponding GPIO
pin will be HIGH (signal lost) when no transitions are detected on the selected input. The
corresponding GPIO pin will be LOW (signal present) when transitions are detected on
the input. The LOS status is also available through the LOS bit in the PLL_STATUS
register, and as a sticky status through the LOS_STICKY bit in the STICKY_STATUS
register at address 50_h.
4.3.2 Lock Detection
The GS6150 lock detection circuitry outputs a LOCKED status signal which indicates that
the CDR has achieved phase lock to the incoming data stream. The LOCKED signal is an
active HIGH output available to the application on any of the GPIO[3:0] multi-function
status and control pins. It is selected for output using the GPIO[3:0]_IO_SELECT and
GPIO[3:0]_SELECT bits accessible in the GPIO_CONTROL_REG_0 and
GPIO_CONTROL_REG_1 registers. By default, LOCKED is output on GPIO1.
The LOCKED status is available from the LOCKED bit in the PLL_STATUS register, and the
LOCK_LOST_STICKY bit in the STICKY_STATUS register indicates whether lock has been
lost since the bit was last cleared.
To optimize systems with high DCD and/or high residual ISI the LOCK_SAMPLE bit of the
PD_CONTROL register should be set to 1_b in conjunction with reducing the Loop
Bandwidth.
GS6150
Final Data Sheet
PDS-060127
Rev.2
March 2015
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