MB85RC256VPF-G Datasheet, PDF (9/36 Pages) Fujitsu Component Limited. – FUJITSU SEMICONDUCTOR

MB85RC256V
• Current Address Read
When the previous write or read operation finishes successfully up to the stop condition and assumes the
last accessed address is “n”, then the address at “n+1” is read by sending the following command unless
turning the power off. If the memory address is last address, the address counter will roll over to 0000H. The
current address in memory address buffer is undefined immediately after the power is turned on.
Access from master
(n+1) address
S 1 0 1 0 A2 A1 A0 1 A
Read
Data 8bits
NP
Access from slave
S Start Condition
P Stop Condition
A ACK (SDA is the "L" level)
N NACK (SDA is the "H" level)
• Random Read
The one byte of data from the memory address saved in the memory address buffer can be read out
synchronously to SCL by specifying the address in the same way as for a write, and then issuing another
start condition and sending the Device Address Word (R/W “1” input).
The final NACK (SDA is the "H" level) is issued by the receiver that receives the data. In this case, this bit is
issued by the master side.
S 1 0 1 0 A2 A1 A0 0 A
Address
High 8bits
A
Address
Low 8bits
A S 1 0 1 0 A2 A1 A0 1 A
Read
Data 8bits
NP
Access from master
Access from slave
S Start Condition
P Stop Condition
A ACK (SDA is the "L" level)
N NACK (SDA is the "H" level)
DS501-00017-3v0-E
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