MB85RC256VPF-G Datasheet, PDF (6/36 Pages) Fujitsu Component Limited. – FUJITSU SEMICONDUCTOR

MB85RC256V
■ DEVICE ADDRESS WORD (Slave address)
Following the start condition, the master inputs the 8 bits device address word to start I²C communication.
The device address word (8 bits) consists of a device Type code (4 bits), device address code (3 bits), and
a read/write code (1 bit).
• Device Type Code (4 bits)
The upper 4 bits of the device address word are a device type code that identifies the device type, and are
fixed at “1010” for the MB85RC256V.
• Device Address Code (3 bits)
Following the device type code, the 3 bits of the device address code are input in order of A2, A1, and A0.
The device address code identifies one device from up to eight devices connected to the bus.
Each MB85RC256V is given a unique 3 bits code on the device address pin (external hardware pin A2, A1,
and A0). The slave only responds if the received device address code is equal to this unique 3 bits code.
• Read/Write Code (1 bit)
The 8th bit of the device address word is the R/W (read/write) code. When the R/W code is “0”, a write
operation is enabled, and the R/W code is “1”, a read operation is enabled for the MB85RC256V.
It turns to a stand-by state if the device code is not “1010” or device address code does not equal to pins
A2, A1, and A0.
• Device Address Word
Start 1 2 3 4 5 6 7 8 9 1 2
SCL
..
SDA
ACK
S ^{1 0 1 0} A2 A1 A0 R/W A
..
Device Code
Device address
Code
Read/Write Code
Access from master
Access from slave
S Start Condition
A ACK (SDA is the "L" level)
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DS501-00017-3v0-E