MB85RC256VPF-G Datasheet, PDF (2/36 Pages) Fujitsu Component Limited. – FUJITSU SEMICONDUCTOR

MB85RC256V
■ PIN ASSIGNMENT
(TOP VIEW)
A0
1
A1
2
A2
3
VSS
4
8
VDD ^A0
7
WP ^A1
6
SCL ^A2
5
SDA ^VSS
(TOP VIEW)
1
8
2
7
3
6
4
5
VDD
WP
SCL
SDA
(FPT-8P-M02)
(FPT-8P-M08)
■ PIN FUNCTIONAL DESCRIPTIONS
Pin
Number
1 to 3
4
5
6
7
8
Pin Name
A0 to A2
VSS
SDA
SCL
WP
VDD
Functional Description
Device Address pins
The MB85RC256V can be connected to the same data bus up to 8 devices.
Device addresses are used in order to identify each of these devices. Connect
these pins to VDD pin or VSS pin externally. Only if the combination of VDD and
VSS pins matches Device Address Code inputted from the SDA pin, the device
operates. In the open pin state, A0, A1, and A2 pins are internally pulled-down
and recognized as the "L" level.
Ground pin
Serial Data I/O pin
This is an I/O pin which performs bidirectional communication for both memory
address and writing/reading data. It is possible to connect multiple devices. It is
an open drain output, so a pull-up resistor is required to be connected to the ex-
ternal circuit.
Serial Clock pin
This is a clock input pin for input/output timing serial data. Data is sampled on
the rising edge of the clock and output on the falling edge.
Write Protect pin
When the Write Protect pin is the “H” level, the writing operation is disabled.
When the Write Protect pin is the “L” level, the entire memory region can be
overwritten. The reading operation is always enabled regardless of the Write
Protect pin input level. The write protect pin is internally pulled down to VSS pin,
and that is recognized as the “L” level (write enabled) when the pin is the open
state.
Supply Voltage pin
2
DS501-00017-3v0-E